The Future of Silicon Scaling


Staff member
Mar 3, 2018
As we've said before, squeezing more performance out of denser silicon chips every few years is becoming a more difficult endeavor. Intel's 10nm process has been nothing but trouble so far, Globalfoundries dropped 7nm because it was too expensive, and TSMC (who are reportedly making AMD's upcoming 7nm chips) is dumping 10s of billions of dollars into research and manufacturing. This week, Semiconductor Engineering talked to several leading figures in the chipmaking and design industries, who had some interesting insights into the future of chip design. Among other things, the finFET transistors Intel pioneered will supposedly "run out of steam" beyond 5nm, meaning the industry will need to look at alternatives like nanosheet and nanowire FETs. Meanwhile, progress is reportedly being made in 3D stacking technology, advanced packaging technologies are becoming more cost effective, and other companies are looking and the possibility of performing some computation in system memory, instead of shuffling it over a high latency, power hungry bus to a different chip.

"In the previous generations, the answer has been that transistor density and Moore's Law will play the lead role to solve computing problems," said Raja Koduri, senior vice president of Core and Visual Computing at Intel. "But as the process node transitions have slowed from the pace of the previous decades, it is the essence of Moore's Law that continues to provide new technologies and capabilities to meet the demands of modern computing. The message of Moore’s Law is about more than transistors alone, with the combination of transistors, architectural research, connectivity advancements, faster memory systems, and software working together to drive it forward..."
It's getting exciting in here. As we approach the performance limit of our current technology, the search for the next breakthrough begins.
I'm wondering if we will end up sitting at a certain process node for a while. If I read what Raja was saying correctly, perhaps the 7/5nm process will start seeing stacked chips/chiplets and such before moving to a die shrink . Like a complete die redesign on how processors work . It will definitely be interesting to see what AMD/Intel will be doing to redefine computing .
Interesting havent heard moveing ram to CPU or move CPU to ram in over a decade.

Would look very different from either but essentially picturing 2-4 sticks of ram each with a small dual or quad core CPU under a big heatspreader that fit into a vertical slot.

Ecc sorta already did this.

Differing Voltage would add alot of complication.
I think from a practical standpoint the interim solution will continue to be more cores and more sockets. Current server tech migrating to the HEDT environment and being marketed at it. Thinking Tyan dual sockets in 2000, Intel Skulltrail in 2008, current Xeon workstation machines. Once my quad core starts feeling slow I'm wondering if my next personal computer will be an Ebay server with a custom loop to keep the sound in check. Software threading will have to improve now that the core wars have driven AMD and Intel crazy.

Stacking has always been a part of the cycle many generations in silicon. I remember back in the 80's when some would stack RAM IC's to increase on the same boards. Nothing majorly wrong, or new, for any of these stop gaps that people are talking about now, it's just a part of the cycle until the next thing.

edit: I actually had a ram kit for an Atari 400 that was 32k and came with 16k we soldered onto to make 48k. Back then that was an achievement for that model.