Rome doubles cache size as expected in Si-Soft ES leak

N4CR

N4CR

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https://www.techpowerup.com/249952/amd-doubles-l3-cache-per-ccx-with-zen-2-rome

Sisoft leak of an ES shows 16mb x 16 per socket for a 2P system, which should mean that it's 2x 16mb cache per chiplet, meaning 4 core CCX is still sadly likely. Or perhaps it counts the IO chip mirroring cache? Thus is a 1x16mb, 8 core CCX...

Very interesting.


rome cache.jpg
 
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I though 8 core CCX was part of the Rome announcement. Or was that simply inferred from the other specifications provided?
 
defaultluser said:
I though 8 core CCX was part of the Rome announcement. Or was that simply inferred from the other specifications provided?
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It was not confirmed, we got very little information about Rome other than the layout and chiplet combination.
 
defaultluser said:
I though 8 core CCX was part of the Rome announcement. Or was that simply inferred from the other specifications provided?
Click to expand...

Each CCX still has 4 cores - they are just shrunk. Each 7nm chiplet package still holds 2x ccx. Since there are 8x 7nm packages on the Rome processor displayed, we get gives us 64 cores/128 threads.
 
Pieter3dnow said:
I thought everything regarding IO was moved onto the 14nm IO block
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Yeah, cache is still on the cpu dies, but all other i/o (main memory/storage/device access) goes through the central die.

Looks like no l4 cache? Hope they just decided it wasn't needed...
 
Nobu said:
Yeah, cache is still on the cpu dies, but all other i/o (main memory/storage/device access) goes through the central die.

Looks like no l4 cache? Hope they just decided it wasn't needed...
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I am guessing L4 cache can be added later on if needed. They'd just hang a pool of static ram off of the IO chip for it.
 
Will it just be EPYC with this separate 14nm IO chip or does this mean TR and Ryzen will have a reduced functionality version???
 
drescherjm said:
Will it just be EPYC with this separate 14nm IO chip or does this mean TR and Ryzen will have a reduced functionality version???
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I suspect both Epyc and the AMD Desktop chips will have the I/O die. The reason I suspect is the same as it was for the Epyc chips - IF, Mem controller and I/O aren't too healthy being built at 7nm so having the larger process chip to deal with them makes sense even on the desktop. I would also venture that AMD will not need to make changes to desktop sockets to accommodate it either.
 
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