Researchers Allegedly Break Write Speed Record With MRAM Test Chip


Staff member
Mar 3, 2018
Researchers from Tohoku University in Japan say they've developed a 128mb MRAM test chip that can achieve a write speed of 14 nanoseconds. The researchers say that's "currently the world's fastest write speed for embedded memory application with a density over 100Mb." The title of the associated paper also mentions that the memory has an endurance "greater than 1010," and that it can retain data for 10 years at 85 degrees Celcius, and the press release says it only need 1.2V to operate. As we've noted before, MRAM has the potential to replace specific uses cases for SRAM, eDRAM, and significantly slower non-volatile storage in the near future, and Intel is supposedly shipping products with 14nm MRAM right now. Thanks to cageymaru for the tip.

STT-MRAM is capable of high-speed operation and consumes very little power as it retains data even when the power is off. Because of these features, STT-MRAM is gaining traction as the next-generation technology for applications such as embedded memory, main memory and logic. Three large semiconductor fabrication plants have announced that risk mass-production will begin in 2018... The current capacity of STT-MRAM is ranged between 8Mb-40Mb. But to make STT-MRAM more practical, it is necessary to increase the memory density. The team at the Center for Innovative Integrated Electronic Systems (CIES) has increased the memory density of STT-MRAM by intensively developing STT-MRAMs in which magnetic tunnel junctions (MTJs) are integrated with CMOS. This will significantly reduce the power-consumption of embedded memory such as cache and eFlash memory.
For comparison: MRAM I use (from eight years ago) 16Mb, 35ns, unlimited nonvolatile writes. Still about $30, not counting DIP adaptor. News is what? 8x bigger, 3x faster.

But if not parallel access (and most offerings today aren't) you may have large latency to set up an address before a series burst of 14nS. Not so great for random access.

SRAMS are still faster, 9nS or something. I havn't checked recently. Cache chips on your old 486 board (28 years ago) were 15nS. Quick if you wanted a forgetful power hog.

Visit Everspin, check spec sheets. Newer MRAM is all accessed by SPI or DDR. Parallel hasn't got a new part in al the time since I bought that 16Mb back whenever.

Gonna want Parallel to make true random access work fast. For existing 16mb part, only one spare ball of 48 limits expansion. 54pin TSOP-II has spares to cover 128Mb.

I have no clue the access method or pinout of the newsy new part, but its on my radar. I would kill for an output 18 bits wide. In my case: for two extra flag bits, not parity.

Give me the third new pin as 21st bit of address, would be the perfect 128Mb. Not saying anyone on that side of the fence likely to pinout for my preference. Cost???
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Some bad math I did there. Widening the data bus from 16 to 18 bits is not the same expansion as two extra bits of address bus. I describe a usage case for only 36Mb.