Gateless Majority Logic

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
692
Photo shows a mix of SSOP and TSOP parts on the front.
For the moment, nothing but empty SOIC pads exist on back.
Individual slices need some wires between those SOIC pads.

Complete assembly might look like eight books on a DIP40 shelf.
A floppy pigtail might bring in power better than rely on DIP pins.

74LVC2G86 XOR gates load the chain about 5pF per slice.
74AUC2G86 XOR could reduce that to about 2.5pF per.
AUC would need a separate 2.7V rail or downregulator, can't
operate at same 5.5V as fastest voltage for CBT multiplexers.

I wonder if emitter followers could help buffer XOR inputs?
KSP10 claims less than 1pF. One base-emitter voltage drop
should be no problem for driving AUC logic's 0.8V threshold.
Even if it slows those final XORs, it might speed up the chain.

I say KSP10 cause I own a bag of 1000 or maybe it was 5000.
Maybe Schottky diodes were the 5000, something was 5000.
Arrow was closing out for under a penny, so why the hell not?
Some kinda gold doped RF transistor that refuses to saturate.
https://www.mouser.com/datasheet/2/149/KSP10-889509.pdf

Left myself no room on these slices to be thinking of buffers.
Where am I supposed to put those? Build as-is and measure.
Maybe there is no problem except I keep changing the plan.

EightSlices.jpg

XOR_MUX_XOR.png
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
692
ManchesterAssymetry.png


An issue of all my prior drawings was the very thin chain of single pass
gates driving cumulative fanout of inactive passages and XOR inputs.
Capacitance multiplied by 16bit length could become a real problem.

Main features of this drawing are parallel passages for the critical path.
That won't make the critical path any faster by itself, only more tolerant
of loads not slowing it down.

Generate and Annihilate logic are now screened off when not in play.
Don't require same ultra-low resistance as main path of Propagation.
Non-paralleled pass gates are preferred here for lower capacitance.
Can't make gates any lower capacitance than they are, but perhaps
make these appear small by comparison.

Was some guy building a 100MHz 6502, though so far only 25MHz.
Had similar chains of CBT3253. Reported measurement of that very
problem, but come to slightly diffferent conclusion how best to solve.

My attempts to contact Drass have not yet worked. Or maybe he has
correctly assessed that all my ideas are nuts and unworthy of reply?
https://c74project.com/
https://hackaday.io/project/174769-100mhz-ttl-6502

Drawing needs fixed again. Borrow backwards should be "Worrob".
Why did I reverse misspell? Nevermind, drawing fixed now...
 
Last edited:

KD5ZXG

Gawd
Joined
Mar 24, 2017
Messages
692
And I just had another useless revelation
while staring too long at this damn borrow
and magnitude chain.

Invert: borrow in, borrow out, result out.
Another way to mutate A-B to B-A when
subtracting. Should work for other ALUs.

As relates to my ALU: I've got two new
subtraction functions to add to the menu.
Can now work with either inverted or non
inverted borrows simply by inverting the
direction at LT GT.

Setup with inverted truth inputs might be
a way to invert the result out, but I kinda
made that difficult by wiring S0 to GND.

Not updating the drawing right now, got
other fires to deal with. Just posting so
I won't forget...
 
Last edited:
Top