AMD RX Vega - Radeon Vega Frontier Die Shot Faked by AMD

FrgMstr

FrgMstr

Just Plain Mean
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AMD has not shared a die shot of it upcoming Vega GPU. You can see the 8 blocks that each hold 8 Next Generation Compute Units which each have 64 stream processors. This gives us a total of 4,096 32-bit floating point units. The blocks you see on bottom are two HMB2 stacks. No comment on die size however, but it is rumored to be over 500mm2. Thanks to Ken for the picture.

So the story, not a real die shot, but a real marketing slide from AMD as we thought, that actually should in fact represent a real die shot...maybe?
 
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I hope it performs well. The world could use some GPU price competition.
 
Zzzzzzz fake news real news it's still not silicon anyone can buy this summer
 
oops...

Wccf just sent me a die shot. Figured I'd post this too.
OId488Z.jpg
 
You should send AMD a nut shot every time they try to pass off their marketing slide images to you as insider info.
 
I mean, it was obviously not a die a shot, it was freaking painted.

But fun marketing i guess.
 
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lolfail9001 said:
I mean, it was obviously not a die a shot, it was freaking painted.

But fun marketing i guess.
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Well yeah, we get that, but at least we can now count it as a realistic graphic representation.
 
Why the heck ppl confusing this with a die shot? It's just a schematic layout of the architecture, like what NV always do with their big green grids..
 
Bahanime said:
Why the heck ppl confusing this with a die shot? It's just a schematic layout of the architecture, like what NV always do with their big green grids..
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Because is AMD. You take a MSpaint image for a granted 100% accurate leak and then blame it on AMD when someone points out the image is an obvious fake.
 
After seeing Threadripper and Epyc, AMD isn't afraid to throw around big dies lately.

I like the idea of silicon so big I have to buy new waterblocks haha
 
Marketing, where all great engineers go to die. Scott had so many years of teasing out legit answers from marketing fluff he is a bonafide expert in non-commitment.
 
I'm just disappointed there aren't more backend ROPs. That has always a weak-point of AMDs.
 
WTF is AMD marketing taking a playbook from Ubisoft? Pre rendered product before actual product. Yet the claim that this is the actual product.
 
DigitalGriffin said:
I'm just disappointed there aren't more backend ROPs. That has always a weak-point of AMDs.
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Why do you think that?

Weaker ROPs would indicate a performance drop off as resolution increases, relatively.

AMD GPUs have historically been the opposite. For example, since 7970, 290X etc, they suffer less performance drop off as resolution increases.

Fury X was a prime example of this, still 64 ROPs (same as 290X), but it runs 4K relatively better than 1080p.
 
Bahanime said:
Why do you think that?

Weaker ROPs would indicate a performance drop off as resolution increases, relatively.

AMD GPUs have historically been the opposite. For example, since 7970, 290X etc, they suffer less performance drop off as resolution increases.

Fury X was a prime example of this, still 64 ROPs (same as 290X), but it runs 4K relatively better than 1080p.
Click to expand...

A ROP is more than a rasterization engine. The measured throughput to the memory is the limiting factor to higher resolutions typically.

The render output unit, often abbreviated as "ROP", and sometimes called (perhaps more properly) raster operations pipeline, is a hardware component in modern graphics processing units (GPUs) and one of the final steps in the rendering process of modern 3D accelerator boards. The pixel pipelines take pixel (each pixel is a dimensionless point), and texel information and process it, via specific matrix and vector operations, into a final pixel or depth value. This process is called rasterization
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The ability to process and discard triangles in the early stages saves those final ROPs from doing extra math in the final stages. For AMD they might do say 150,000 in a small block. For the same scene and the same block, NVIDIA might process 100,000 ops because they have less triangles to process through early discard. Combine this with the fact NVIDIA generally has more ROPs, you get what I'm getting at. So yeah there might be plenty of bandwidth to handle higher resolutions but you are processing more than you have to.

Owning a 7970 one of it's strengths was the fact it had such a wide bus to help with bandwidth. Same with the FuryX (High bandwidth) But the backend rops are still doing more math than necessary.
 
DigitalGriffin said:
A ROP is more than a rasterization engine. The measured throughput to the memory is the limiting factor to higher resolutions typically.



The ability to process and discard triangles in the early stages saves those final ROPs from doing extra math in the final stages. For AMD they might do say 150,000 in a small block. For the same scene and the same block, NVIDIA might process 100,000 ops because they have less triangles to process through early discard. Combine this with the fact NVIDIA generally has more ROPs, you get what I'm getting at. So yeah there might be plenty of bandwidth to handle higher resolutions but you are processing more than you have to.

Owning a 7970 one of it's strengths was the fact it had such a wide bus to help with bandwidth. Same with the FuryX (High bandwidth) But the backend rops are still doing more math than necessary.
Click to expand...

If you're talking about memory bandwidth efficiency, that's the Tile-based Rasterization technique which NV has used since Maxwell, keeping things on their L2 cache instead of wasting VRAM bandwidth..

So if Vega uses that, along with it's discard features, and the other L2/ROP change, it stands to reason 64 Vega ROPs would be much more effective than 64 Fury X or 290X ROPs.
 
Well i refuse to believe that anyone on this or any other tech forum is stupid enough to think that layout illustration is actually a die shot. So if not stupid then trolling?
 
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